Ok, I just submitted this on the GSoC website as a proposal: https://google-melange.appspot.com/gsoc/proposal/review/google/gsoc2013/jase...
Here's a full quote of the proposal's text: -----%<----- Currently there is no nice open source electronics CAD tool. The largest competitors are gEDA which I find awkward to use and KiCad which I find even more awkward to use. Since a schematics editor is not much more than a special-purpose flow graph editor and a PCB layout editor is in fact nothing but a somewhat crippled vector graphics editor with some special-purpose features added I think it is very promising to modify a general purpose vector graphics editor to support the few special-purpose functions additionally required by an electronics CAD tool.
I wrote a detailed list of the missing parts at the spec page on the Inkscape wiki. For GSoC I will concentrate on two features: A "component" abstraction and netlist generation.
A component is a reusable object like the schematic symbol of a capacitor, resistor or IC or the footprint of a particular package on the circuit board that can be inserted into a document from a library. Internally, a component looks much like a group that can span multiple layers and has some metadata (part number, voltage rating etc.) attached to it. The library will probably just map to some folders on the disk. A component template may be a "static" component, i.e. a simple SVG file whose content will be pasted into the document when the component is inserted, or a "dynamic" component, a special python extension that generates SVG based on some parameters. This concept is actually very similar to the existing "new from template" blueprint (that is currently not being worked on).
The component feature is generic enough to be very useful outside of electronics CAD.
A netlist is a description of which component on the schematic or circuit board is connected to which other component. It is needed to map from schematic to board layout and to check for errors in the board layout (like two touching or crossing traces). Netlist generation is a pretty brute-force process, tough this is not a problem since it is only performed infrequently. I will implement netlist generation and mapping from schematic to board layout (this step is not too hard since the components share identifies on both).
The netlist feature is also useful outside of electronics CAD, e.g. to select all objects that touch the selected object and have the same color ("select everything part of this blue area").
Timeline Week -3 to -2 Acclimatize with the source. Get commit access by doing the required few basic patches Week -1 Look into the details of the affected code areas and write some doc Week 0 to 2 Write the component abstraction as described in the linked spec document Week 3 to 4 Templates and template library Week 5 Integrate into mainline Week 6 to 10 Write the netlist feature as described in the spec document Week 11 Integration into mainline -----%<-----